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Design-Reuse11h
5G Ultra low power Sub-6 GHz RF Transceiver IP
This is a 3GPP compliant 5G Sub-6GHz RF Transceiver IP optimized for cellular application. It integrates all the necessary RF/analog/mixed signal functions for a 3GPP Universal/5G/4G/3G 2x2 ...
Design-Reuse11h
TSMC 6nm (6FF) 3.3V GPIO
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their SoCs targeting mobile, automotive, and ...
Design-Reuse11h
TSMC 3nm (N3E) 1.2V/1.8V GPIO Libraries
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their SoCs targeting mobile, automotive, and ...
Design-Reuse11h
Single Port Register File compiler - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 40 kbits
Single Port Register File compiler - TSMC 90 nm uLL - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 40 kbits View Single Port Register File compiler - Memory ...
Design-Reuse13h
PCIe 4.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
Rambus PCIe 4.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The Rambus PCIe 4.0 Controller is compliant with the PCI Express 4.0 and ...
Design-Reuse14h
14-bit, 300 MSPS Ultra Low Power ADC in 28nm CMOS
The ODT-ADP-14B300M-28 is a low power high speed pipelined ADC designed in a 28nm standard CMOS process, implemented using Omni Design's groundbreaking low power SWIFT technology. This 14-bit ADC ...
Design-Reuse14h
800MHz, 12-bit High Speed Delta Sigma ADC for 5G, LiDAR and Imaging
The SM-CTDSM-800M is a 12-bit continuous-time delta-sigma (CTΔΣ) analog-to-digital converter IP. By leveraging Seamless’ patented Switched-Mode Signal Processing (SMSP) technology, our ADC seamlessly ...
Design-Reuse14h
PCIe Gen3 to SRIO Gen3 Bridge (FPGA)
Mobiveil’s PCIe Gen3 to SRIO Gen3 Bridge is a high-performance FPGA-based protocol conversion IP that enables seamless communication between PCI Express (PCIe) and Serial RapidIO (SRIO) systems.
Design-Reuse14h
Die-to-Die, High Bandwidth Interconnect PHY in TSMC (N7, N5)
The Synopsys High-Bandwidth Interconnect PHY IP enables high bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and networking applications.
Design-Reuse14h
Universal Chiplet Interconnect Express (UCIe) Controller
Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The IP also enables latency-optimized NoC-to-NoC ...
Design-Reuse14h
40G UCIe PHY IP on Samsung SF4X
Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI, and networking applications. The PHY’s flexible ...