Semiconductor Engineering

Raising The Bar On Flat CDC Verification With Hierarchical Data Models

Traditionally, clock domain crossing (CDC) verification at the SoC level has relied on flat simulation runs. But flat CDC verification has run out of gas. Largely because of the increase in the number ...
JSTOR Daily

A Hierarchical Model for Compositional Data Analysis

Mark J. Brewer, João A. N. Filipe, David A. Elston, Lorna A. Dawson, Robert W. Mayes, Chris Soulsby and Sarah M. Dunn This article introduces a hierarchical model for compositional analysis. Our ...
JSTOR Daily

Analyzing multilevel data: comparing findings from hierarchical linear modeling and ordinary least squares regression

This study examined the differing conclusions one may come to depending upon the type of analysis chosen, hierarchical linear modeling or ordinary least squares (OLS) regression. To illustrate this ...
EDN

ATopTech Introduces Industry’s First Top-Level Design Tool to Seamlessly Integrate All Hierarchical Functions with Block-Level Implementation

San Francisco, CA – July 27, 2009 — ATopTech, Inc., the primary technology leader in integrated circuit (IC) physical design solutions addressing the challenges of designing ICs at 65 nanometers and ...